This invention relates generally to single event upset (SEU) hardening of latch circuits, and, more particularly to single event upset (SEU) circuits comprised of two cross-coupled inverters.
Circuit designs which provide improved tolerance to SEU are known, see U.S. Pat. No. 4,683,570 to Bedard et al. titled xe2x80x9cSelf Checking Digital Fault Detector for Modular Redundant Real Time Clockxe2x80x9d, issued Jul. 28, 1987; and U.S. Pat. No. 5,031,180 titled xe2x80x9cTriple Redundant Fault-Tolerant Registerxe2x80x9d to McIver et al., issued Jul. 9, 1991. The aforementioned two U.S. patents teach the use of triple redundancy with the outputs connected to three voting circuits which provide feedback to the logic circuit. In Bedard et al., voter circuitry provides an output which is used for failure detection and power-up reset. Bedard et al. being intended for a real time clock. McIver et al. provides SEU hardening for a register by employing triple redundant master slave clocked mux circuitry, each voter circuitry output providing feedback to the output of its slave mux.
In contrast to the preceding prior art, in the present invention the voter output circuitry is fed back to the output mode of the latch circuit instead of the input to the latch. The present single event upset hardened latch circuit, in further contrast includes a voter output circuit which provides increased drive of the output latch circuit. The present latch circuit comprises a novel design hardening approach which is focused at mitigating the effect of SEU at the transistor level rather than the IC output level. This unique design for CMOS or NMOS memory or latch circuits comprises two cross-coupled inverters.